1. Field of the Invention
The present invention relates to a method for forming wirings on a semiconductor device and, more particularly, to a method of forming multilayer wiring thereon.
2. Description of the Related Art
A description will subsequently be given of a conventional method of forming multilayer wiring in a semiconductor integrated circuit. A wiring conductor such as aluminum is first deposited to form a first-layer wiring by sputtering on a semiconductor substrate provided with semiconductor elements formed thereon, an insulating film such as a CVD SiO.sub.2 film grown on the elements and contact holes in the insulating film. The photoetching technique is then used for patterning the wiring conductor for the first-layer wiring including lower wirings, element electrodes and seats for through-holes. Subsequently, an interlevel insulating film is grown by, e.g., the plasma CVD method and through-holes are bored by photoetching above the seats. An upper-layer wiring conductor is thereafter deposited by sputtering and then patterned by photoetching to form upper wirings and connections to the seat of the first-layer wiring through the through-holes, whereby the upper and lower wirings are connected via the through-holes.
In addition to the formation of the interlevel insulating film by the plasma CVD method, there has been proposed, as in Japanese Patent Application Laid-Open Nos. 100748/1982, 124246/1983 and a technical periodic "Semiconductor World", No. 10, 1984, pp 129-133, ibid. No. 3, 1987, pp 36-42, the provision of a multilayer insulating film comprising a glass film formed by the coating method and an insulating film by the CVD method or the provision of an SiO.sub.2 film by coating with an organic silicon compound.
In the conventional method of forming the multilayer wiring, however, the unevenness of the sublayer and the lower wiring layer is generally reflected on the surface of a single-phase plasma CVD film when the plasma CVD film is employed as the interlevel insulating film. The film-forming properties in the stepped lower wiring layer portion under the upper wiring layer will be harmfully affected by the lower-layer wiring conductor if it is made more than 1.0 .mu.m thick, which will result in low reliability. In addition, it becomes hardly possible to micronize the wire-to-wire space of the lower wiring layer.
Although the application of the glass film formed by the coating method or that of the organic silicon compound to the whole or part of the interlevel insulating film ensures excellent flatness on condition that the thickness of the film formed by the coating method is set greater than that of the lower wiring layer, the film-coated layer is exposed at the time the through-hole for connecting the upper and lower wiring layers is bored to cause corrosion of the wiring conductors due to outgassing of, e.g., H.sub.2 O accompanied by the dehydrating condensation reaction of the coating film therefrom. If the interlevel insulating film is made thick enough to maintain the interlayer insulation, the depth of the through-hole tends to increase; the disadvantage in this case is that the coverage of the through-hole portion in the upper wiring layer deteriorates.
Moreover, there has also been proposed, as in "NIKKEI MICRODEVICES", No. 1, 1988, p 19, a method of forming an upper wiring layer, the method comprising the steps of pre-forming aluminum pillars for connecting upper and lower wirings layers on the lower wiring layer, coating the whole surface with polyimide as an interlevel insulating film and exposing the head of each aluminum pillar by etching. However, this method requires very complicated manufacturing steps.